1. Field of Invention
The present invention relates to a semiconductor device and a fabricating method thereof, and more particularly to a CMOS device and a fabricating method thereof.
2. Description of Related Art
In the development of integrated circuit devices, the objects of high speed operation and low power consumption can be achieved by reducing the size of the device. However, since the technology of reducing the device size is limited by such factors as technique bottlenecks and expensive costs, other techniques for reducing the size of the device are desired to improve the driving current of the device. Therefore, it is proposed that the limitation of the device be overcome by using stress control in the channel area of the transistor. The method is by changing the space between the Si lattices through stress, so as to increase the mobility of electrons and holes, thereby improving the performance of the device.
A conventional method for enhancing the device performance by stress control is by using a silicon nitride layer as a contact etch stop layer (CESL) to generate stress, thus increasing the drive current of the device, to achieve the object of enhancing the device performance. However, when the tensile stress of the silicon nitride layer increases, the drive current of the n channel area increases, but the drive current of the p channel area decreases. On the contrary, when the compressive stress of the silicon nitride layer increases, the drive current of the p channel area increases, but the drive current of the n channel area decreases. In other words, the method for enhancing the transistor performance by using a silicon nitride layer to generate stress can only be used to improve the performance of the N-type MOS transistor or the performance of the P-type MOS transistor, but cannot improve the performances of the N-type MOS transistor and the P-type MOS transistor simultaneously.
In U.S. Pat. No. 6,573,172 B1, a method for improving the performance of N-type MOS transistor and P-type MOS transistor is provided. First, an N-type MOS transistor and a P-type MOS transistor are formed on a substrate, and a shallow trench isolation (STI) structure is formed there-between to isolate the N-type MOS transistor and the P-type MOS transistor. Then, a first silicon nitride layer is deposited to cover the whole substrate. Next, a patterned photoresist layer is formed on the first silicon nitride layer to expose the first silicon nitride layer on the N-type MOS transistor. Thereafter, an etching process is performed using the patterned photoresist layer as a mask, to remove the exposed first silicon nitride layer, and meanwhile the first silicon nitride layer on the P-type MOS remains. Then, the patterned photoresist layer is removed. Subsequently, an oxide layer is formed on the substrate to cover the first silicon nitride layer and the N-type MOS transistor. Then, a second silicon nitride layer is deposited in the same way to cover the whole substrate. Next, the second silicon nitride layer on the P-type MOS transistor is removed, while the second silicon nitride layer on the N-type MOS transistor is kept. Thus, silicon nitride layers having tensile stress and compressive stress can be formed respectively on the N-type MOS transistor and the P-type MOS transistor. Therefore, the object of simultaneously improving the performances of the N-type MOS transistor and the P-type MOS transistor can be achieved.
However, although the above method can simultaneously improve the performance of the N-type MOS transistor and the P-type MOS transistor, some problems still remain. For example, after the silicon nitride layer not covered by the photoresist layer is removed, the photoresist layer is generally removed by bumping the photoresist layer with oxygen plasma. However, in such way, the exposed film layers and components, e.g. spacers, metal silicide, and silicon dioxide layer and nickel silicide layer without STI structure of the transistor area, are easily damaged, thus affecting the performance and reliability of the device.